`timescale 1ns / 1ps

module xmj_LFSR_3bit(
	input wire CLK,
	input wire RST,
	output reg[2:0] Q
);
	
	always @(posedge CLK or posedge RST) begin
		if(RST) Q <= 3'b001;
		else Q <= {Q[1:0], Q[2] ^ Q[0]};
	end
	
endmodule
